Bidirectional voltage differentiator circuit

ABSTRACT

A bidirectional voltage differentiator circuit comprises start-up circuitry, sensing circuitry, and output circuitry coupled to logic circuitry. The start-up circuitry acts to start-up the sensing circuitry when the circuit is powered on, and accelerates the response of the sensing circuitry thereafter. The sensing circuitry senses variation in an input voltage applied to an input node. Responsive to the voltage variation sensed by the sensing circuitry, the output circuitry produces a state change at a first or second output node. The logic circuitry receives the states of the output nodes and produces a logic output signal to indicate the occurrence of the variation sensed in the input voltage. The voltage sensing circuit is operable to sense variation of the input voltage regardless of whether the voltage is rising or falling and without regard to the DC value of the input voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application from U.S. application forpatent Ser. No. 13/648,412 filed Oct. 10, 2012, which claims priorityfrom Chinese Application for Patent No. 201110461949.8 filed Dec. 31,2011 and from Chinese Application for Patent No. 201210268942.9 filedJul. 27, 2012, the disclosures of which are hereby incorporated byreference.

BACKGROUND

1. Technical Field

The present invention relates generally to voltage sensing circuitryand, more particularly, to an integrated circuit operable to sensebidirectional variation of an input voltage and produce an output signalindicating the occurrence of said voltage variation.

2. Introduction

Traditional voltage sensing circuits require circuitry for sensing afirst voltage variation in one direction (e.g., rising) and additionalcircuitry for sensing a second voltage variation in another direction(e.g., falling). The additional circuitry required to sense a voltagechange reduces efficiency of the circuit and requires additionalcomponents, thereby increasing manufacturing costs. Additionally, manytraditional voltage sensing circuits consider a DC component of thesensed voltage, which may otherwise be unnecessary and further reduceefficiency of the circuit. Accordingly, there exists a need for voltagesensing circuitry with improved efficiency that may be manufactured atreduced expense.

SUMMARY

An integrated bidirectional voltage differentiator circuit is presentedfor sensing bidirectional variation of an input voltage and producing anoutput signal indicating the occurrence of said voltage variation. Inone embodiment, the bidirectional voltage differentiator circuitcomprises: first circuitry operable to sense a change in an inputvoltage; second circuitry operable, in response to said first circuitrysensing a first change in said input voltage, to change a state of afirst logic signal and, in response to said first circuitry sensing asecond change in said input voltage, to change a state of a second logicsignal; and third circuitry operable, in response to a change in saidfirst logic signal state or a change in said second logic signal state,to produce a third signal indicative of said first circuitry sensingsaid change in said input voltage.

In another embodiment, the bidirectional voltage differentiator circuitcomprises: a voltage differentiator circuit operable to sense andrespond to a positive change in an input voltage by increasing currentapplied to first circuitry operable to generate a state change of afirst output signal, and further operable to sense and respond to anegative change in said input voltage by decreasing said current appliedto said first circuitry operable to generate a state change of a secondoutput signal; and second circuitry operable, in response to said firstand second output signals, to produce a third signal indicative of asensed change in said input voltage.

In yet another embodiment, the bidirectional voltage differentiatorcircuit comprises: a current generator circuit comprising: an input nodecapacitively coupled to a first circuit leg; a first internal outputnode coupled to said first circuit leg; and a second internal outputnode coupled to a second circuit leg; first pull-down circuitry having afirst control node coupled to said first internal output node; secondpull-down circuitry having a second control node coupled to said secondinternal output node; and logic circuitry coupled to said firstpull-down circuitry at a first logic output node, and coupled to saidsecond pull-down circuitry at a second logic output node.

The foregoing and other features and advantages of the presentdisclosure will become further apparent from the following detaileddescription of the embodiments, read in conjunction with theaccompanying drawings. The detailed description and drawings are merelyillustrative of the disclosure, rather than limiting the scope of theinvention as defined by the appended claims and equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example in the accompanyingfigures not necessarily drawn to scale, in which like reference numbersindicate similar parts, and in which:

FIG. 1 illustrates a first example embodiment of a bidirectional voltagedifferentiator circuit in accordance with the present disclosure;

FIG. 2 illustrates a timing diagram corresponding to the disclosedbidirectional voltage differentiator circuit illustrated in FIG. 1;

FIG. 3 illustrates simulation results for the bidirectional voltagedifferentiator circuit shown in FIG. 1;

FIGS. 4A and 4B illustrate additional example embodiments of abidirectional voltage differentiator circuit in accordance with thepresent disclosure;

FIG. 5 illustrates an application of the bidirectional voltagedifferentiator circuit to sense voltage of an LED panel; and

FIG. 6 illustrates a waveform for a typical panel voltage Vpanel in anAMOLED panel and a timing diagram for the logic states of the outputsignals for the bidirectional voltage differentiator circuit.

DETAILED DESCRIPTION

FIG. 1 illustrates a bidirectional voltage differentiator circuit 100 inaccordance with an example embodiment of the present disclosure. Thedisclosed bidirectional voltage differentiator circuit 100 comprisesstart-up circuitry 110, sensing circuitry 130, and output circuitry 150coupled to logic circuitry 170. The start-up circuitry 110 acts tostart-up the sensing circuitry 130 in a current-generating state whenthe circuit 100 is powered on, and accelerates the response of thesensing circuitry 130 thereafter. The sensing circuitry 130 sensesvariation in an input voltage VIN applied to an input node IN.Responsive to the voltage variation sensed by the sensing circuitry 130,the output circuitry 150 produces a state change at a first output nodeOUT1 or at a second output node OUT2. The logic circuitry 170 receivesthe states of OUT1 and OUT2 and produces a logic output signal OUTZ toindicate the occurrence of the variation sensed in the input voltageVIN. The disclosed voltage sensing circuit 100 is operable to sensevariation of the input voltage VIN regardless of whether the voltage VINis rising or falling and without regard to the DC value of the inputvoltage VIN.

The components comprising the respective start-up circuitry 110, sensingcircuitry 130, output circuitry 150, and logic circuitry 170 are brieflydescribed in the following paragraphs with reference to the circuit 100illustrated in FIG. 1, wherein the operation of the circuit 100 isdescribed in greater detail thereafter. The start-up circuitry 110includes a first current mirror 112 comprised of transistors MS4 andMS5. Transistor MS5 is coupled to a current sink (not shown) at abiasing node 113 to provide a biasing current I_(Bias) from transistorMS5. Transistor MS4 may be sized to transistor MS5 to set a mirroredbias current I_(Bias), which is supplied to node 115. The currentsupplied to node 115 produces a voltage VA1 for turning on accelerationcircuitry 116. The acceleration circuitry 116 is comprised ofseries-connected transistors MR1, MR2, MR3, and MR4. The voltage VA1 isapplied to the gates of the respective transistors MR1, MR2, MR3, andMR4. Accordingly, the bias current I_(Bias) from transistor MS5 shouldbe great enough to generate a voltage VA1 large enough to turn ontransistors MR1-MR4, thus activating the acceleration circuitry 116.When activated, the acceleration circuitry 116 supplies a current I_(A)at node 120 to supply additional current to accelerate response of thesensing circuitry 130, as further explained below. In an exampleembodiment of the circuit 100, I_(Bias)=2.5 uA, (W/L)_(MS5)=(10 u/5u)*2, (W/L)_(MS4)=(10 u/5 u)*2, and the combined size of transistors MR1through MR4 may be represented as (W/L)_(MR1-MR4)=(1 u/35 u).

The circuit 100 further includes a second current mirror 114 comprisedof transistors MS2 and MS3, wherein the drain of transistor MS3 iscoupled to node 115, and the drain of transistor MS2 is coupled to atransistor MS1. Transistor MS1 is responsive to the voltage at node 120to control a current I_(MS2) at transistor MS2, wherein transistor MS2may be sized to transistor MS3 to set current I_(MS3), which is drawnfrom node 115. At start-up, the transistor MS1 is turned off, whichresults in a low I_(MS3). When the voltage at node 120 produces a V_(GS)voltage greater than the threshold voltage of transistor MS1, transistorMS1 is activated and the current I_(MS3) is drawn from the node 115.Accordingly, the current I_(Bias)′ should be large enough to providesufficient voltage VA1 to activate the acceleration circuitry 116 whentransistor MS1 is initially off at start-up, and to maintain activationof the acceleration circuitry 116 thereafter. Therefore, after start-upof the circuit 100, the acceleration circuitry 116 will continue to drawcurrent from node 120. In an example embodiment of the circuit 100illustrated in FIG. 1, (W/L)_(MS3)=(10 u/5 u)*2, (W/L)_(MS2)=(10 u/5u)*2, and (W/L)_(MS1)=(10 u/5 u)*10.

As illustrated in FIG. 1, the sensing circuitry 130 comprisestransistors M1, M2, M3, and M4, resistor R1, and a sensing capacitor CS1coupled to the input node IN. The sensing capacitor CS1 blocks the DCcomponent of the input voltage VIN applied to the input node IN, andpasses variation of the input voltage VIN to the circuit 100 as voltageVCS1. In accordance with the present disclosure, the sensing circuit 130has two operating states. The first operating state (i.e., the quiescentstate) occurs when there is no variation in the input voltage VIN. Inthis quiescent state, an initial sensing capacitor voltage VCS1 isapplied to transistors M1-M4 and substantially no additional current isapplied to transistors M1-M4 from the input node IN. The secondoperating state occurs when there is a variation in the input voltageVIN and a corresponding change in the voltage VCS1 causes a change inthe current flowing through transistors M1-M4. In accordance with anembodiment of the present disclosure, when the sensing capacitor CS1senses a positive change, or increase, in the input voltage VIN, thecurrents across respective transistors M1-M4 increase. When the sensingcapacitor CS1 senses a negative change, or decrease, in the inputvoltage VIN, the currents across respective transistors M1-M4 decrease.

Transistors M2 and M4 are coupled together to form a first leg of thesensing circuitry 130, wherein the sensing capacitor CS1 is coupled to anode located between the drain of transistor M2 and the drain oftransistor M4 as illustrated in FIG. 1. Additionally, transistor M2 iscoupled to transistors M5 and M11 to form a third current mirror 132,and transistor M4 is coupled to transistors M3, M6, M9, and MS1 to forma fourth current mirror 134, wherein the fourth current mirror 134 iscoupled to node 120 at the drain of transistor M3 and the gate oftransistor MS1.

Transistors M1 and M3 are coupled together to form a second leg of thesensing circuitry 130. The drain of transistor M1 is coupled to node 120which, as previously mentioned, is coupled to the acceleration circuitry116 and to the gate of transistor MS1. The gate of transistor M1 iscoupled to the gate of transistor M2, and the source of transistor M1 iscoupled to resistor R1. Resistor R1 sets the current across transistorM1 (I_(M1)), which is reflected about the third and fourth currentmirrors 132 and 134. Accordingly, the resistor R1 regulates the DCcurrent of transistors M1-M4 to provide a quiescent state current ateach of the transistors M1-M4. In the embodiment illustrated in FIG. 1,the resistor R1 regulates the current of transistors M1-M4 such that achange in current across transistor M2 is greater than a change incurrent across transistor M3 (i.e., ΔI_(M2)>ΔI_(M3)). It should beappreciated that, in other embodiments, the resistor R1 mayalternatively be coupled to other components such as, for example, thesource of transistor M4. In an example embodiment of the circuit 100illustrated in FIG. 1, CS1=16 pF, R1=120 kOhms, (W/L)_(M1)=(10 u/5u)*14, (W/L)_(M2)=(10 u/5 u)*8, (W/L)_(M3)=(10 u/5 u)*10, and(W/L)_(M4)=(10 u/5 u)*10.

The output circuitry 150 includes a fifth current mirror 152 comprisedof transistors M7 and M8, a sixth current mirror 154 comprised oftransistors M10 and M12, transistors M6 and M9 (which are included inthe fourth current mirror 134), transistors M5 and M11 (which areincluded in the third current mirror 132), the first output node OUT1,and the second output node OUT2. The drain of transistor M5 is coupledto the drain of transistor M6 at the first output node OUT1. In theembodiment illustrated in FIG. 1, the size of transistor M6 is equal tothe size of transistor M4 (e.g., (W/L)_(M6)=(W/L)_(M4)=(10 u/5 u)*10),the size of transistor M2 is larger than the size of transistor M5(e.g., (W/L)_(M2)=(10 u/5 u)*8 and (W/L)_(M5)=(10 u/5 u)*6), and thesize of transistor M4 is larger than the size of transistor M9 (e.g.,(W/L)_(M4)=(10 u/5 u)*10 and (W/L)_(M9)=(10 u/5 u)*8). During thequiescent state, I_(M3)=I_(M4)=I_(M2), and the current across M6(I_(M6)) is driven higher than the current across M5 (I_(M5)), therebydriving the state of the first output node OUT1 high during thequiescent state.

The drain of transistor M9 is coupled to the fifth current mirror 152 atthe drain and gate of transistor M7, wherein transistor M7 may be sizedto transistor M8 to set current I_(M8). The drain of transistor M11 iscoupled to the sixth current mirror 154 at the drain and gate oftransistor M12, wherein transistor M12 may be sized to transistor M10 toset current I_(M10). The second output node OUT2 is coupled betweentransistor M8 of the fifth current mirror 152 and transistor M10 of thesixth current mirror 154. During the quiescent state, the current acrosstransistor M11 (I_(M11)) is greater than the current across transistorM9 (I_(M9)). Therefore, during the quiescent state, I_(M10) drives thestate of the second output node OUT2 high. In an example embodiment ofthe circuit 100 illustrated in FIG. 1, (W/L)_(M7)=(10 u/5 u)*4,(W/L)_(M8)=(10 u/5 u)*4, (W/L)_(M10)=(10 u/5 u)*4, (W/L)_(M11)=(10 u/5u)*8, and (W/L)_(M12)=(10 u/5 u)*4.

As shown in FIG. 1, the logic circuitry 170 comprises a NAND gate 172having inputs coupled to respective output nodes OUT1 and OUT2, andproducing an active high output logic signal OUTZ. As described ingreater detail below, the output logic signal OUTZ is provided toindicate the occurrence of a variation or transition of the inputvoltage VIN applied at the input node IN. Although a NAND gate producingan active high output signal is provided in the embodiment describedherein, it should be understood that alternative embodiments maycomprise other circuitry that may be active high or low withoutdeparting from the spirit and scope of the present disclosure as setforth in the claims provided below.

Operation of the circuit 100 is now described in greater detail withreference to both the circuit 100 illustrated in FIG. 1 and thecorresponding timing diagram 200 illustrated in FIG. 2. The timingdiagram 200 illustrates operation of the circuit 100 by providing logicstates of the OUT1, OUT2, and OUTZ signals in response to an example VINsignal 205. The timing diagram 200 shows a first stage 202 wherein thevoltage VIN is low with no variation, a second stage 204 wherein VIN isincreasing, a third stage 206 wherein VIN is high with no variation, afourth stage 208 wherein VIN is decreasing, and a fifth stage 210wherein VIN is low with no variation.

During the first stage 202, the voltage VIN is low with no variation andthe circuit 100 is in the quiescent state. During the quiescent state,both the first output node OUT1 and the second output node OUT2 arehigh, therefore, the output logic signal OUTZ is low.

During the second stage 204, the voltage VIN increases (i.e., changesfrom a lower voltage to a higher voltage). The sense capacitor CS1senses the variation in the voltage VIN, which causes a correspondingchange in the current across respective transistors M1-M4. As thevoltage VIN increases, the currents across transistors M2 (I_(M2)) andM3 (I_(M3)) increase. The change in current across M2 is larger than thechange in current across M3 (i.e., ΔI_(M2)>ΔI_(M3)), and the currentacross transistor M5 (I_(M5)) becomes greater than the current acrosstransistor M6 (I_(M6)), which pulls output node OUT1 low. Therefore, asthe voltage VIN transitions from low to high, OUT1 goes low while OUT2remains high, thus causing OUTZ to go high during the second stage 204.

During the third stage 206, the voltage VIN remains high with novariation. Accordingly, I_(M6) again becomes greater than I_(M5), andthe circuit 100 returns to the quiescent state. Since there is novariation of VIN during the third stage 206, OUT1 returns to a highstate, and OUTZ returns to a low state.

During the fourth stage 208, the voltage VIN decreases (i.e., changesfrom a higher voltage to a lower voltage). As the voltage VIN decreases,I_(M2) and I_(M3) decrease. The change in I_(M2) is greater than thechange in I_(M3), and the current across transistor M8 (I_(M8)) becomeslarger than the current across transistor M10 (I_(M10)), which pullsoutput node OUT2 low. Therefore, as the voltage VIN transitions fromhigh to low, OUT2 goes low while OUT1 remains high, thus causing OUTZ togo high during the fourth stage 208.

During the fifth stage 210, the voltage VIN remains low with novariation. As further described below, the acceleration circuitry 116accelerates the recovery of the sensing circuitry 130, and the circuit100 again returns to the quiescent state. Accordingly, OUT2 returns to ahigh state, and OUTZ returns to a low state. As illustrated in FIG. 2,the OUTZ signal is low when there is no variation of the voltage VIN onthe input node IN, and is high when the voltage VIN is varying ortransitioning, regardless of the DC value of the voltage on IN. Thus,the logic output signal OUTZ may be used to indicate the occurrence of avariation of the input voltage VIN.

Recovery of the sensing circuitry 130 is further described herein withreference to the start-up circuitry 110 and sensing circuitry 130illustrated in FIG. 1. As previously mentioned, the start-up circuitry110 is operable to start-up the sensing circuitry 130 (in acurrent-sensing mode) once the circuit 100 is powered on, and is furtheroperable to accelerate the response of the sensing circuitry 130thereafter. As the voltage VIN on the input node IN decreases (see e.g.,fourth stage 208 in FIG. 2), current flows out of the input node IN,thus causing the voltage VCS1 to decrease. As VCS1 decreases, I_(M2) andI_(M3) decrease, which causes I_(M8) to become greater than I_(M10) andpulls OUT2 low as described above. Once the voltage VIN has finisheddecreasing, no current flows from the input node IN. At this point,I_(M3) and I_(M4) try to recharge the capacitor CS1 at the current setby transistor M1 to drive the voltage VCS1 back to its quiescent state,which also drives OUT2 from low to high. However, since the capacitorCS1 may be relatively large, this recovery may be slow and thetransition of OUT2 from low to high may be significantly delayed. Thedelayed transition of OUT2 results in a delayed change in the logicoutput signal OUTZ, wherein during this delayed transition period, thelogic output signal OUTZ is incorrectly indicating a voltage variationat the input node IN. Therefore, in order to accelerate the recovery ofthe capacitor CS1 and voltage VCS1, the start-up circuitry 110 usesacceleration circuitry 116 to increase the currents across resistors M3and M4 (I_(M3) and I_(M4), respectively) to charge capacitor CS1 andthereby decrease the recovery time. By decreasing the recovery time, thestart-up circuitry 110 reduces the delay from when the input voltage VINstops decreasing and the second output node OUT2 returns to itsquiescent state. Thus, the duration of the incorrect output of the logicoutput signal OUTZ is significantly reduced.

In order to accelerate the recovery of sensing capacitor CS1, theacceleration circuitry 116 draws additional current I_(A) from node 120.The additional current I_(A) is mirrored by the fourth current mirror134, which causes I_(M3) and I_(M4) to supply additional current to thesensing capacitor CS1, thereby accelerating the charging of CS1 andreducing the time required for VCS1 to reach its quiescent state.

Operation of the disclosed bidirectional voltage differentiator circuit100, including the acceleration functionality, is further illustrated bythe simulation results 300 illustrated in FIG. 3. In the simulationshown in FIG. 3, VIN increases from zero to 12V with a 64 us rising timeand decreases from 12V to 8V with a 20 us falling time. In general, whenVIN is increasing or decreasing, OUTZ is logic high, and when VIN isconstant, OUTZ is logic low. As shown in FIG. 3, the logic output signalOUTZ changes states when the input voltage varies by approximately0.12V. Additionally, after VIN increases, the falling OUTZ signal isdelayed by approximately 2 us while OUT1 returns to its quiescent state,and after VIN decreases, the falling OUTZ signal is delayed byapproximately 7 us while OUT2 returns to its quiescent state.

It should be appreciated by one of ordinary skill in the art that theembodiment disclosed herein is provided to illustrate one example forimplementing a bidirectional voltage differentiator circuit inaccordance with the present disclosure. As such, variations to thecircuit illustrated in FIG. 1 may be made without departing from thespirit or scope of the present disclosure as set forth in the claimsprovided below. For example, FIGS. 4A and 4B illustrate additionalimplementations of the disclosed bidirectional voltage differentiatorcircuit.

Reference is now made to FIG. 5 which illustrates an application of thebidirectional voltage differentiator circuit (FIG. 1, 4A or 4B) to sensevoltage of an LED panel. A circuit 300 for use with an LED panel 302(such as an AMOLED (active-matrix organic light-emitting diode) panelknown to those skilled in the art) comprises a power MOSFET 304 having adrain terminal coupled to a supply voltage Vsupply. The MOSFET 304includes a gate terminal coupled to receive a control signal. The sourceterminal of the MOSFET 304 produces a panel voltage Vpanel and iscoupled to the LED panel 302 (which those skilled in the art willrecognize has an associated panel capacitance Cpanel).

It is important in operation of the LED panel 302 to determine thefinish of power transmission. This occurs, for example, when the panelvoltage Vpanel equals the supply voltage Vsupply, or when the panelvoltage Vpanel equal some other known voltage. Prior art configurationsinserted a sense resistor between the panel voltage Vpanel node and thesource terminal of the MOSFET 304 in order to sense current flow to/fromthe panel. However, with an AMOLED panel there is a large current in thepower MOSFET 304 which makes it difficult to add the prior art senseresistor configuration.

The bidirectional voltage differentiator circuit, in any of theimplementations discussed above in FIGS. 1, 4A and 4B, can beadvantageously used to sense voltage of the LED panel. The VIN inputnode of the bidirectional voltage differentiator circuit is coupled tothe source terminal of the MOSFET 304 which produces the panel voltageVpanel. Thus, VIN will equal Vpanel. The state transitions of the OUT1,OUIT2 and OUTZ signals will then provide information indicative of theturning on of the MOSFET 304, power transmission to/from the panel 302,and finish of power transmission with respect to the panel 302.

Reference is now made to FIG. 6 which illustrates a waveform for atypical panel voltage Vpanel in an AMOLED panel and the timing diagramfor logic states of the output signals for the bidirectional voltagedifferentiator circuit. As discussed above, the bidirectional voltagedifferentiator circuit operates as a slope detector. The OUT1 signaltransitions from a first logic state to a second logic state in responseto an increase in voltage at the input VIN (positive slope detection),and transitions from the second logic state to the first logic state inresponse to termination of voltage increase. Thus, where VIN=Vpanel, atransition of the OUT1 signal from the first logic state to the secondlogic state indicates an increase in the panel voltage Vpanel, while atransition in the OUT1 signal from the second logic state to the firstlogic state indicates that the increase in panel voltage has terminated.In an AMOLED panel configuration with MOSFET 304, the transition of theOUT1 signal from the first logic state to the second logic stateaccordingly indicates the start of power transmission to the panel,while the transition in the OUT1 signal from the second logic state tothe first logic state indicates the finish of power transmission to thepanel, such as when Vpanel=Vsupply. The OUTZ signal will accordinglytransition from the second logic state to the first logic state at thebeginning of power transmission to the panel, and transition from thefirst logic state to the second logic state at the finish of powertransmission to the panel.

The foregoing describes operation in connection with a powertransmission with a positive slope. FIG. 6 further illustrates that thebidirectional voltage differentiator circuit will also operate to makepower transmission detection when the power transition has a negativeslope. The OUT2 signal transitions from a first logic state to a secondlogic state in response to a decrease in voltage at the input VIN(negative slope detection), and transitions from the second logic stateto the first logic state in response to termination of voltage decrease.Thus, where VIN=Vpanel, a transition of the OUT2 signal from the firstlogic state to the second logic state indicates a decrease in the panelvoltage Vpanel, while a transition in the OUT2 signal from the secondlogic state to the first logic state indicates that the decrease inpanel voltage has terminated. In an AMOLED panel configuration withMOSFET 304, the transition of the OUT2 signal from the first logic stateto the second logic state accordingly indicates the start of powertransmission from the panel, while the transition in the OUT2 signalfrom the second logic state to the first logic state indicates thefinish of power transmission from the panel, such as when Vpanel=VIN2.The OUTZ signal will accordingly transition from the second logic stateto the first logic state at the beginning of power transmission from thepanel, and transition from the first logic state to the second logicstate at the finish of power transmission from the panel.

When there is no variation in panel voltage Vpanel, the OUTZ signal isstays at the second logic level. The OUTZ signal can thus be used totrigger detection of power transmission completion. However, during anyvariation in panel voltage (positive or negative, and indicative ofpower transmission with respect to the panel), the OUTZ signaltransitions to the first logic level and stays at the first logic levelfor as long as panel voltage variation (power transmission) continues.The OUTZ signal can thus be used to trigger slope control operations forthe panel. Specifically, when the OUTZ signal transitions to the firstlogic level (indicative of a sensed slope change at the VIN node), thislogic state can be detected by a control circuit for the panel and usedto trigger actions taken to control the rate of change (i.e., a slopecontrol mode of operation).

What is claimed is:
 1. A circuit for controlling operation of a displayincluding an LED panel and a drive transistor that is configured toprovide a supply voltage for the LED panel, comprising: a detectioncircuit coupled to receive the supply voltage and configured to sense afirst slope change in said supply voltage and change a state of a firstlogic signal during at least a duration of said first slope change andconfigured to sense a second slope change in said supply voltage andchange a state of a second logic signal during at least a duration ofsaid second slope change; and an output circuit configured to generatean output signal, in response to the change in state of either the firstlogic signal or the second logic signal, that is indicative of saiddetection circuit sensing either the first or second slope change insaid supply voltage.
 2. The circuit of claim 1, wherein said first slopechange is an increase in said supply voltage, the circuit furtherconfigured to perform slope control of the supply voltage until saidsupply voltage increases to a high voltage level.
 3. The circuit ofclaim 2, wherein said detection circuit further senses a third slopechange corresponding to said slope control and maintains the changedstate of the first logic signal during a duration of said third slopechange.
 4. The circuit of claim 2, wherein said change in state of thefirst logic signal is indicative of a start of drive transistor powertransmission to the LED panel.
 5. The circuit of claim 1, wherein saidsecond slope change is a decrease in said supply voltage, the circuitfurther configured to perform slope control of the supply voltage untilsaid supply voltage decreases to a low voltage level.
 6. The circuit ofclaim 5, wherein said detection circuit further senses a third slopechange corresponding to said slope control and maintains the changedstate of the second logic signal during a duration of said third slopechange.
 7. The circuit of claim 5, wherein said change in state of thesecond logic signal is indicative of a finish of drive transistor powertransmission to the LED panel.
 8. The circuit of claim 1, wherein saiddetection circuit includes a blocking circuit configured to block a DCcomponent of said supply voltage.
 9. The circuit of claim 1, whereinsaid detection circuit includes a sense circuit configured to sense saidfirst slope change in said supply voltage and further includes arecovery circuit configured to reduce a recovery time of said sensecircuit after said sense circuit senses said second change in saidsupply voltage.
 10. The circuit of claim 9, wherein said recoverycircuit comprises acceleration circuitry operable to produce a chargingcurrent applied to a capacitor of said sense circuitry.
 11. The circuitof claim 10, wherein said acceleration circuitry comprises a pluralityof series connected transistors.
 12. The circuit of claim 10, whereinsaid recovery circuit is operable to reduce a delay time of said outputsignal.
 13. The circuit of claim 1, wherein said detection circuitcomprises a first transistor coupled in series with a second transistor,wherein a current across said first transistor becomes greater than acurrent across said second transistor when said detection circuit sensessaid first change in said supply voltage.
 14. The circuit of claim 13,wherein said first logic signal changes state when said current acrosssaid first transistor is greater than said current across said secondtransistor.
 15. The circuit of claim 1, wherein said detection circuitcomprises a first transistor coupled in series with a second transistor,wherein a current across said first transistor becomes greater than acurrent across said second transistor when said detection circuit sensessaid second change in said supply voltage.
 16. The circuit of claim 15,wherein said second logic signal changes state when said current acrosssaid first transistor is greater than said current across said secondtransistor.
 17. The circuit of claim 1, wherein said detection circuitcomprises a capacitor coupled between a first current mirror and asecond current mirror.
 18. The circuit of claim 1, wherein a logic stateof said third signal is indicative of sensing power transmission by thedrive transistor to the LED panel.
 19. The circuit of claim 1, whereinthe detection circuit comprises: a voltage differentiator circuitoperable to sense and respond to a positive change in the supply voltageby increasing current applied to first circuitry operable to generatethe state change of the first logic signal, and further operable tosense and respond to a negative change in said supply voltage bydecreasing said current applied to said first circuitry.
 20. The circuitof claim 19, wherein said first circuitry comprises a first currentmirror operable, in response to said increase of said current, togenerate said state change of said first logic signal.
 21. The circuitof claim 20, wherein said first current mirror comprises a firsttransistor operable, in response to said increase of said current, topull said first logic signal state low.
 22. The circuit of claim 20,wherein said first circuitry further comprises a second current mirroroperable, in response to said decrease of said current, to generate saidstate change of said second logic signal.
 23. The circuit of claim 22,wherein said second current mirror comprises a second transistoroperable to pull said first logic signal state high.
 24. The circuit ofclaim 22, wherein said second current mirror comprises a thirdtransistor operable, in response to said decrease of said current, tocontrol a third current mirror to pull said second logic signal statelow.
 25. The circuit of claim 22, wherein said voltage differentiatorcircuit further comprises a capacitor coupled between said first currentmirror and said second current mirror, said capacitor operable to blocka DC component of said supply voltage.
 26. The circuit of claim 20,wherein said first current mirror further comprises a fourth transistoroperable to control a fourth current mirror to pull said second outputsignal state high.
 27. The circuit of claim 19, wherein said voltagedifferentiator circuit further comprises a biasing transistor coupled inseries with a resistor.
 28. The circuit of claim 19, further comprisinga recovery circuit operable to reduce recovery time of said voltagedifferentiator circuit after said voltage differentiator circuit sensessaid change in said supply voltage.
 29. The circuit of claim 28, whereinsaid recovery circuit comprises a plurality of series connectedtransistors.
 30. The circuit of claim 1, implemented as an integratedcircuit.